X5-210M - Innovative Designs X5-210M - PCI Express XMC Module with Four...
- Part Number:
- X5-210M
- Model Number:
- X5-210M
- Make:
- INNOVATIVE INTEGRATION
- Lead Time:
- Available
- Qty In Stock:
- Available
Innovative Designs X5-210M - PCI Express XMC Module with Four 250 MSPS 14-bit A/Ds, Virtex5 FPGA, and DDR2/QDR-II Memory Simple Type: Mezzanine Card
The X5-210M is an XMC IO module featuring four 14-bit 250 MSPS A/Ds with a Virtex5 FPGA computing core, DRAM and SRAM memory, and eight lane PCI Express host interface. A Xilinx Virtex5 SX95T with 512MB DDR2 DRAM and 4MB QDR-II memory provide a very high performance DSP core for demanding applications such as emerging wireless standards. The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates exceeding 300 GMACs per second. The X5 XMC modules couple Innovative's powerful Velocia architecture with a high performance, 8-lane PCI Express interface that provides over 1 GB/s sustained transfer rates to the host. Private links to host cards with > 1.6 GB/s capacity using P16 are provided for system integration. The X5 family can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator. Software tools for host development include C++ libraries and drivers for Windows and Linux. Application examples demonstrating the module features and use are provided.
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Features
- +/-1V, 50 ohm, SMA inputs and outputs
- >1 GB/s, 8-lane PCI Express Host Interface
- 4 MB QDR-II SRAM
- 512 MB DDR2 DRAM
- 8 RocketIO private links, 2.5 Gbps each
- Adapters for VPX, Compact PCI, Desktop PCI and Cabled PCI Express Systems
- Four 250 MSPS 14-bit A/D channels
- PCI Express (VITA 42.3)
- Power Management features
- Ruggedization Levels for Wide Temperature Operation
- Xilinx Virtex5, SX95T
- XMC Module (75x150 mm)
Specifications
- A/D Sample Rate: 1 MHz to 250 MHz
- A/D Resolution: 14-bit
- DRAM Controller: Controller for DRAM implemented in logic. DRAM is controlled as a single bank.
- DRAM Rate: 3.8 GB/ sustained transfer rate
- DRAM Size: 512 MB total, 4 devices @ 64Mx16 each
- DRAM Type: DDR2 DRAM
- FPGA Block RAMs: SX95T: 296 (5328 Kbits) LX155T: 212
- FPGA Configuration: SelectMAP from on-board flash EEPROM - JTAG during development
- FPGA Device: Xilinx Virtex5, XC5VSX95T-1FF1136C, XC5VLX155T-1FF1136C
- FPGA Flip-Flops: SX95T: 69120, LX155T : 97280
- FPGA Multipliers: SX95T: 640, LX155T: 680
- FPGA Rocket IO: 16 lanes @ 2.5 Gbps
- FPGA Size: SX95T :~9M gate equivalent, LX155T :~15M gate equivalent
- FPGA Slice: SX95T: 17,280, LX155T: 24,320
- FPGA Speed Grade: -1 (commercial)
- Input Impedance: 50 ohm
- Input Range: +/- 1V
- Input Type: Single ended, DC coupled
- Inputs: 4
- SRAM Controller: Two independent SRAM controllers implemented in FPGA logic
- SRAM Rate: 1.2 GB/s sustained transfer rate for read and write simultaneously (2.4 GB/s total)
- SRAM Size: 4 MB total, 2 devices @ 512Kx32 each
- SRAM Type: QDR-II
Applications
- None Available
Aliases
- None Available
