X5-400M - Innovative Integration X5-400M - PCIe XMC Module - Two 400...
- Part Number:
- X5-400M
- Model Number:
- X5-400M
- Make:
- INNOVATIVE INTEGRATION
- Lead Time:
- Available
- Qty In Stock:
- Available
Innovative Integration X5-400M - PCIe XMC Module - Two 400 MSPS, 14-bit TI ADS5474 ADCs and Two 500 MSPS, 16-bit DACs, Virtex5 FPGA and 512 MB Memory Simple Type: Mezzanine Card
The X5-400M is an XMC IO module featuring two 14-bit, 400 MSPS A/D and two 16-bit, 500 MSPS DAC channels with a Virtex5 FPGA computing core and PCI Express host interface on a standard XMC module. A Xilinx Virtex5 SX95T FPGA with 512 MB DDR2 DRAM and 4MB QDR-II memory provide a very high performance DSP core for demanding applications such as emerging wireless standards. The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates exceeding 300 GMACs per second. The X5 XMC modules couple Innovative's powerful Velocia architecture with a high performance, 8-lane PCI Express interface that provides over 1 GB/s sustained transfer rates to the host. Private links to host cards with > 1.6 GB/s capacity using J16 are provided for system integration. The X5 family can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator. Software tools for host development include C++ libraries and drivers for Windows and Linux. Application examples demonstrating the module features and use are provided.
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Features
- +/-1V, 50 ohm, SMA inputs and outputs
- >1 GB/s, 8-lane PCI Express Host Interface
- 4 MB QDR-II SRAM
- 512 MB DDR2 DRAM
- 8 Rocket IO private links, 2.5 Gbps each
- Adapters for VPX, Compact PCI, Desktop PCI and Cabled PCI Express Systems
- PCI Express (VITA 42.3)
- Power Management features
- Ruggedization Levels for Wide Temperature Operation
- Two 400 MSPS, 14-bit A/D channels
- Two 500 MSPS, 16-bit DAC channels
- Xilinx Virtex5, SX95T FPGA
- XMC Module (75x150 mm)
Specifications
- A/D Sample: Rate 20 MHz to 400 MHz (lower rates must use decimation in logic)
- A/D Device: Texas Instruments ADS5474
- A/D Resolution: 14-bit
- Calibration: Factory calibrated. Gain and offset errors are digitally corrected in the FPGA. Non-volatile EEPROM coefficient memory.
- Connectors: SMA female
- DAC Device: Texas Instruments DAC5687
- DAC Interpolation: Programmable 2-8x
- DAC Resolution: 16-bit
- DAC Sample Rate: 16 MHz to 500 MHz, depending on mode
- Data Format: 2's complement, 16-bit integer
- DRAM Controller: Controller for DRAM implemented in logic. DRAM is controlled as a single bank.
- DRAM Rate: 4.2 GB/s storage/retrieval rate sustained
- DRAM Size: 512MB total 4 devices @ 64Mx16 each
- DRAM Type: DDR2 DRAM
- FPGA 18Kb Block RAMs: SX95T: 488 LX155T: 424
- FPGA Configuration: SelectMAP from on-board flash. EEPROM - JTAG during development
- FPGA Device: Xilinx Virtex5, XC5VSX95T, XC5VSX155T
- FPGA Flip-Flops: SX95T : 58880 LX155T : 97280
- FPGA FPGA Usage (Framework Logic): SX95T: LUT
- FPGA Multipliers: SX95T: 640 LX155T: 128
- FPGA Rocket IO: 16 lanes @ 2.5 Gbps
- FPGA Size: SX95T: ~9M gate equivalent LX155T: ~15M gate equivalent
- FPGA Slices: SX95T: 17,280 LX155T: 24,320
- FPGA Speed Grade: -1 or -2
- Input Impedance: 50 ohm
- Input Range: +/- 1V
- Input Type: Single ended, AC or DC coupled
- Inputs: 2
- Max Output Current: 95 mA
- Max Safe Input Voltage: -5.7V to +5.7V
- Output Impedance: 50 ohm
- Output Range: +/- 1V
- Output Type: Single ended, DC coupled
- Outputs: 2
- SRAM Controller: Two independent SRAM controllers implemented in FPGA logic
- SRAM Rate: 3.2 GB/s storage/retrieval max rate sustained
- SRAM Size: 4 MB total 2 devices @ 512Kx32 each
- SRAM Type: QDR-II
Applications
- None Available
Aliases
- None Available
